TEXAS INSTRUMENTS ADS7869 handbook(2) Pdf (2024)

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1. 3 5 3 6 3 7 3 8 3 9 3 10 vi 3 4 4 Mode 11 Bus Access TMS320c54xx DSP Family Compatible Mode Register Map s cascade ata ador ette x en tasa ee bacs bre beta Med Register Descriptions eR denne 3 6 1 FIFO Data Register 00 isse tk PERE ES be ees 3 6 2 Offset Registers 01 to OCH 3 6 3 Gain Registers to 18y 3 6 4 WINDAC Register 19 3 6 5 Control Register 3 6 6 Counter Control Status Register 1BH 3 6 7 Edge Count Register 1Cy 1Dy 20 21 3 6 8 Edge Period Register 1 and 229 3 6 9 Edge Time Period Register 1 and 23y 3 6 10 FIFO Test Register 24H 3 6 11 Comparator Test Register 25H 3 6 12 Interrupt Register 265 3 6 13 Parallel Register 27H 3 6 14 Reset Registe
2. 7 Position Sensor Comparator Overdrive 8 Current Sign Comparator Overdrive 9 Typical Transfer Function of a Window Comparator 10 S Eo S o T m E 1 12 Continuous SPI Transfer 2 2 113 SPI ACCESS s ae 1 14 Mode 10 Read Access 1 15 Mode 10 Write ACCESS a a 1 16 Mode 11 Read Access Standard Mode 1 17 Mode 11 Write Access Standard 1 18 Mode 11 Read Access TMS320c54xx mode RR eed xenon 1 21 FIFO Block Diagrams a Au Badia USED I EF agentes 1222 Timing of the DAV Signal aranana Rer e ded 1 23 Block Diagram of a Counter Module 1 24 Digital Noise Filter Block Diagram
3. Unused read as 0 don t care at write DAV The 8 bits input to Digital to Analog Converter 1 DAV signal active HIGH 0 DAV signal active LOW 12 0 Input channel selection bits 000 AN3 for ADC3 001 AX for ADC BX for and AN3 for ADC3 010 A2 via SH4 for ADC4 B2 via SH3 for ADC2 and AN2 for ADC3 011 A2 via SH2 for ADC4 B2 via SH4 for ADC2 and AN2 for ADC3 100 101 110 A1 for ADC for ADC2 and AN1 for ADC3 111 IU for IV for ADCo and IW for ADC3 41 Analog Motor Control Front End with Simultaneous Sampling on Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs Texas ADS7869 INSTRUMENTS SBAS253E MAY 2003 REVISED JULY 2006 3 6 6 Counter Control Status Register 1B The Counter Control Status Register is located in address The counter control status register CCTRLSTAT is a combined control register for the filtered input of the counters and a status register for the over or under flow status of the counters and the filtered input signals strobed by HOLD1 See the Digital Counters section for more information on this topic When the filter bits FxxE are set the appropriate input is synchronized with the system clock and a digital filter processes the input signal If the bit is reset the signals are just synchronized The overflow states EOx TOx are set when the appropriate counter has reached the value FFFFy This indicates when the time between
4. 0 13 1 3030 3031 3032 3033 Code decimal Figure 1 5 Histogram of 8000 Conversions 2 3 Sign Comparators ADS7869 includes two sets of sign comparators that differ in their hysteresis The first set which is used for the position sensor inputs in motor control applications is connected to the inputs A1 B1 A2 and B2 The hysteresis of these comparators is typically 75mV In motor control applications these comparators are used to measure the signs of the position sensor input signals The second set is in parallel to the window comparators at the U_C V_C and W_C pins The hysteresis of these components is typically 10mV In motor control applications these comparators are used to measure the sign of the main currents The sign comparator switches from 0 to 1 if the differential input voltage is above 1 2 of the hysteresis If the output is 1 the sign comparator switches back to 0 if the differential input voltage is below 1 2 of the hysteresis See Figure 1 6 Half Hysteresis OV Half Hysteresis Comparator if Output Figure 1 6 Typical Transfer Function of a Sign Comparator Analog Motor Control Front End with Simultaneous Sampling on 4 Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs TEXAS ADS7869 INSTRUMENTS SBAS253E MAY 2003 REVISED JULY 2006 The input range of the comparators is limited The lower voltage of the differential inputs should always be within the range of 0
5. 5V PARAMETER SYMBOL UNT Delay time from CS LOW to output data not in tri state mode o p m Delay time from address not valid to output data not valid tx 0 15 Delay time from CS HIGH to output data in tri state mode o tbs 8 n 1 All input signals are specified with tR tF Sns 10 to 90 of BVpp and timed from a voltage level of VIL VIH 2 2 One or more read cycles can be performed in one CS cycle Figure 1 18 Mode 11 Read Access TMS320c54xx mode 35 Analog Motor Control Front End with Simultaneous Sampling on Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs WO Texas www ti com SBAS253E MAY 2003 REVISED JULY 2006 3 442 Write Timing Characteristics 1 Over recommended operating free air temperature range at 40 C to 85 C AVpp 5V BVpp 3V 5V PARAMETER Setup ine rom RAVLOW a CS LOW ww 0 9 s time fom CS HIGH e HIGH 8 e Setup ime tom address vaide tow ww 0 CCAS Setuptme datavaldtoCSHIGH For OS HIGH to datanotwa 1 All input signals are specified with tR tp 5ns 10 to 90 of BVpp and timed from a voltage level of 2 Figure 1 19 Mode 11 Write Access TMS320c54xx mode 36 ag Motor Control Front End with Simultaneous Sampling on Texas Seven S H Capacitors and Three 1MSPS 12 Bit 12 Chan
6. 205 sanr RR RT RES Ries Host Parallel Port Operation Register Map Write 16 bit 4 Register Map Read 16 bit 2 1 12 FFO Output Word d es 1 13 Offset Registers as eomm x ret Ru eer ten et trs e Rue UR Rs RR RE headed weds 1215 WINDAG Register E S Ne ER E LE ERES 1216 Control cz eri bees RR RET RF eae tees bb 1 17 Counter Control Status Register 1 18 Synchronous Latched Edge Count Register 1 19 Asynchronous Latched Edge Count Register 1 20 Edge Period Register s red tant tebe anak en e e p dw ee 1 21 Edge Time Period Register 1 22 FIFO Test Register ees Sree REPRE S ESPERE oe alee RI DIN at wees 1 23 Comparator Test Registe
7. Table 1 1 Selection of Interface Mode Parallel 2 As a function of the selected mode some pins will have different assignment as shown in Table 1 2 Table 1 2 Mode vs Pin Functions Pin No Mode Parallel 1 Parallel 2 80 81 sor a V Sic 598 re 598 9 No Aw ADDR rant is iss 5 U DATA2 DATA3 DATA4 n oo e ois o 68 ADOUT3 ADOUT3 SPISOMI 6 ADIN ADIN SPISIMO DATA8 DATA8 a DATAS DATAS DATA10 DATA10 DATA11 DATA11 DATA12 DATA12 DATA13 DATA13 DATA14 DATA14 Nc E o e 59 3 89 7 x O DAV ADBUSY HOLDI ADCONV 86 HOLD2 NPSH HOLD2 HOLD2 HOLD2 1 NC means no connection The NC pins in 1 and SPI modes should be grounded with a pull down resistor 2 For parallel mode 11 there is one sub mode for compatibility with the TMS320c54xx DSP family see Mode 11 Bus Access TMS320c54xx DSP family compatible mode section 3 Original VECANAO 1 pin names 23 Analog Motor Control Front End with Simultaneous Sampling on Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs WO Texas www ti com SBAS253E MAY 2003 REVISED JULY 2006 3 2 VECANA
8. compensation 00 T o 1 02 value channel B2 included offset and compensation 00 T 9 channel IW included offset gain compensation 00 00H 0 ADC3 value channel AN2 included offset and gain compensation ahr fof oasis no ta gancomp 00 1 0 ADCj value channel AX included offset and gain compensation ahr 11 secre 00 1 o 9 00 1151 2 00 00 49 Analog Motor Control Front End with Simultaneous Sampling on S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs NEAS AD 7869 www ti com SBAS253E MAY 2003 REVISED JULY 2006 The DAV signal becomes active when the write pointer is ahead of the read pointer The DAV signal becomes inactive again when the read pointer equals the write pointer that is when the FIFO is empty When the ADCs are writing data into the FIFO and the write pointer is more than 32 steps ahead of the read pointer a FF FIFO Full state will be set FF is cleared when the first FIFO read operation is performed To synchronize the pointers after an FF state the FIFO should be read out until a FE FIFO Empty occurs If a read is attempted while the read and write pointers are equal the read pointer will not increase the same data the data with the same channel number is read again When this occurs an FE state is set The FE state is cleared whe
9. EDGECNT2 over or under flow did not occur TO2F Time counter 2 TIMECOUNT2 over or under flow flag 1 TIMECOUNT2 over or under flow occurred 0 TIMECOUNT 2 over or under flow did not occur EO1F Edge counter 1 EDGECNT1 over or under flow flag 1 EDGECNT1 over or under flow occurred 0 EDGECNT1 over or under flow did not occur Time counter 1 TIMECOUNT1 over or under flow flag 1 TIMECOUNT1 over or under flow occurred 0 TIMECOUNT1 over or under flow did not occur Bit 7 6 Unused read as 0 46 pna og Motor Control Front End with Simultaneous Sampling on Texas Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs INSTRUMENTS ADS7869 SBAS253E MAY 2003 REVISED JULY 2006 Interrupt Register continued FF FIFO full state 1 FIFO is full 0 FIFO is not full FE FIFO empty state 1 FIFO is empty 0 FIFO is not empty FFF FIFO full flag 1 FIFO is or was full 0 FIFO is not or was not full FEF FIFO empty flag 1 FIFO is or was empty 0 FIFO is not or was not empty FFE FIFO full interrupt enable bit 1 Interrupt enable 0 Interrupt disable FEE FIFO empty interrupt enable bit 1 Interrupt enable 0 Interrupt disable 3 6 13 Parallel Register 27 The Parallel Register in address 27 controls the parallel interface mode 11 see the Mode 11 Bus Access sections The Parallel Register has no effect on modes 00 01 and 10 There is only one bi
10. 1 1 1 i 1 1 oj Oj 5B Readeounierconrerandsausregser 38 i pna og Motor Control Front End with Simultaneous Sampling on INSTRUMENTS Seven S H Capacitors and Three 1MSPS 12 Bit 12 15 SBAS253E MAY 2003 REVISED JULY 2006 3 6 Register Descriptions The following table shows the symbols that are used in this section The last number in the symbol represents the reset value Value After Reset The clock has to be running when the registers in the register map are accessed 3 6 1 FIFO Data Register 00 The FIFO Data Register is at address 00 in the register map The output word of the FIFO is in16 bit format The resolution of the ADCs is 12 bits Output data from each of the ADCs is in binary two s complement format The four MSBs are used for channel identification The format of the output word is shown in Table 1 12 There are three words stored in the FIFO for each conversion There must be three read accesses to this register to get all three conversion values out of the FIFO Table 1 12 FIFO Output Word Format mcm we mco memorem ium m m ow ow ow Dio 5 ba 57 o 5 pris stis otis oma eir oio prs l CA3 0 INPUT CHANNEL ADDRESS BITS 0000 Data from IU input 0001 Data from 1 input 0010 Data from A2 input 0011 Data from IV input 0100 Data from B1 input 0101 Da
11. ADDR lt 0 5 gt REFOUT Y Aa v Figure 1 2 Functional Diagram 15 Analog Motor Control Front End with Simultaneous Sampling on Seven S H Capacitors and Three MSPS 12 Bit 12 Channel ADCs WO Texas www ti com SBAS253E MAY 2003 REVISED JULY 2006 2 2 1 2 1 1 16 Analog Section The analog section addresses the Analog to Digital Converters including the gain and offset adjustment There is also a discussion of the analog inputs the seven sign comparators three window comparators the 8 bit Digital to Analog Converter DAC the reference voltage grounding and the supply voltage Fully Differential Analog Inputs Analog to Digital Converter Inputs The 12 inputs to the ADCs as well as the three inputs U_C V_C and W_C to the comparators are fully differential and provide a good common mode rejection of 60dB at 50kHz This is very important to suppress noise in difficult environments The seven sample and hold circuits from the ADC contain a 5pF capacitor Cg in Figure 1 3 that is connected via a switch to the analog inputs Opening the switch holds the data The switch closes when the conversion is finish
12. Input Select 34 A2 is converted by ADC on the signal HOLD1 A2 is sampled on SH in a preceding conversion with Input Select 44 5 or 64 B2 is converted by ADC on the signal HOLD1 B2 is sampled SH in a preceding conversion with Input Select 44 5 or 64 AN2 is sampled by the synchronous sample and hold 5 5 converts it on the signal HOLD1 Input Select 44 5 and 6 A1 is sampled by the synchronous sample and hold SH ADC converts it on the signal HOLD1 B1 is sampled by the synchronous sample and hold SH3 converts it on the signal HOLD1 is sampled by the synchronous sample and hold SHs5 ADC converts it on the signal HOLD1 A2 is sampled by the synchronous sample and hold SH on the signal HOLD1 B2 is sampled by the synchronous sample and hold SH4 on the signal HOLD1 25 Analog Motor Control Front End with Simultaneous Sampling on Seven S H Capacitors and Three 1 5 5 12 Bit 12 Channel ADCs YO Texas 0 ADS7869 www ti com SBAS253E MAY 2003 REVISED JULY 2006 Input Select 7 IU is sampled by the synchronous sample and hold SH4 ADC converts it on the signal HOLD1 IV is sampled by the synchronous sample and hold SH3 ADC converts it on the signal HOLD1 IW is sampled by the synchronous sample and hold 5 5 ADC converts it on the signal HOLD1 3 222 VECANA Timing Characteristics 1 Over recommended operating free air temperature range at 40
13. Page numbers for previous revisions may differ from page numbers in the current version Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 17 Oct 2006 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Type Drawing Qty ADS7869IPZT ACTIVE TQFP PZT 100 90 Green RoHS amp NIPDAU Level 4 260C 72 HR no Sb Br ADS7869IPZTG4 ACTIVE TQFP PZT 100 90 Green RoHS amp NIPDAU Level 4 260C 72 HR no Sb Br ADS7869IPZTR ACTIVE TQFP PZT 100 1000 Green RoHS amp NIPDAU Level 4 260C 72 HR no Sb Br ADS7869IPZTRG4 ACTIVE TQFP PZT 100 1000 Green RoHS amp NIPDAU Level 4 260C 72 HR no Sb Br The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free RoHS Pb Free RoHS Exempt or Green RoHS amp no Sb Br please check http Awww ti com productcontent for the latest availability information and additional p
14. 1 1 25 Timing Diagram of the Counter Signals with the Digital Noise Filter Enabled 1 26 Timing Diagram of the Counter Signals with the Digital Noise Filter Disabled 1 27 Detail Counter Block gt 1 28 Detail Counter Timing 1 29 Timing Diagram of the Reset Signal vii Analog Motor Control Front End with Simultaneous Sampling on Seven 5 Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs Texas 2 www ti com SBAS253E MAY 2003 REVISED JULY 2006 List of Tables Selection of Interface Mode vs Pin FUNCIONS ede ER EE edd DAC Input Output Relationships VECANA Gain Select Information 13 bit VECANA ADIN Word Controls for Input Multiplexers and Sample Window Comparator Clock 4 SPI Write 24 bit Word Format
15. 27 and the timing is shown in Figure 1 28 U D signal is high counting upwards when B1 runs before A1 The U D signal is low counting downwards when A1 runs before B1 The EDGE signal is set by every filtered edge of A1 and B1 16 Bit Register LE 16 Bit UP DN Binary Counter ASEDGCNT 16 Bit Register CNT EDGECNT LE SYEDGCNT 16 Bit UP DN 16 Bit 16 Bit Binary Counter Register Register LE TIMECOUNT EDGEPRD SYEDGPRD 16 Bit Register LE SYEDGTIME Figure 1 27 Detail Counter Block Diagram 56 i pna og Motor Control Front End with Simultaneous Sampling on INSTRUMENTS Seven S H Capacitors and Three 1MSPS 12 Bit fee 15 SBAS253E MAY 2003 REVISED JULY 2006 When EDGECNT cause an over or under flow the corresponding bit in the Interrupt Register is set The counter continues to increment or decrement in value When the EDGE signal rises the TIMECOUNT value is latched into the shadow register EDGEPRD The value of EDGEPRD is the number of system clocks between two valid edges of the input signals from the comparators This value is reciprocally proportional to the angular speed of the position sensor The value in the EDGEPRD register is latched in the SYEDGPRD Register on the synchronous hold signal HOLD1 The EDGECNT and TIMECOUNT counter values are stored into the shadow registers SYEDGCNT and SYEDGPRD with the synchronous hold signal HOLD1 which samples the an
16. 5 3 Applies for 3 0V nominal supply 2 7V lt BVpp lt 3 6V Analog Motor Control Front End with Simultaneous Sampling on Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs Texas ADS7869 INSTRUMENTS SBAS253E MAY 2003 REVISED JULY 2006 1 6 PINOUT DRAWING TQFP Package 2 2 lt lt 94 93 192 91 REFOUT CNTB1 HOLD1 gt lt 2 86 85 84 83 81 80 79 DATAO DATA1 DATA2 DATAS3 DATA4 DATAS DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 ADS7869 DATA12 DATA13 DATA14 DATA15 oy AIl py m 1 Jf IS IS I IS Im 1S ial PO ILS Por 42 43 144 145146 147 148 49 150 25 27 6 m a 46 a gt ana og Motor Control Front End with Simultaneous Sampling on Texas Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs INSTRUMENTS ADS7869 SBAS253E MAY 2003 REVISED JULY 2006 1 7 PIN FUNCTIONS TQFP Package ANALOG SIGNALS Analog Input Signals of Position Sensors 8 Poston Sensor X Asynchronous Analog Input of SIN Negative m _Aralogin Postton Sensor 2 Analog Input of IN Negative pt Position Sensor 2 Analog Input of COS Positive Input Position Sensor 2 Analog Input of COS Negative Input Position Sensor X Asynchronous Analog Input of COS Positive Input Position Sensor X Asynchr
17. AD 7869 www ti com SBAS253E MAY 2003 REVISED JULY 2006 One 16 bit transfer is accomplished as follows 1 On the first falling edge of SPICLK the read write bit is strobed On the third falling edge of SPICLK the MSB of the address bit 5 is strobed On the eighth falling edge of SPICLK the LSB of the address bit 0 is strobed and the corresponding data of the register map is read 4 On the ninth rising edge the data read from the register is latched into a shift register and shifted one position each rising edge of the SPICLK This data is always sent out even when a write operation is performed 5 the 24th falling edge of SPICLK the last data bit is shifted from SPISIMO and a write pulse is generated to write the data into the register map if a write operation was performed During continuous read or write see Figure 1 12 the address is decrementing after each read or write see the indicating arrows When the address is set to 00 in the beginning the FIFO can be read out fast The data is written into the register map on the 16th SPICLK of a data word If the SPISTE is inactive before the 16th SPICLK in a data word the data is not written into the register map therefore the data is lost SPISTE SPICLK 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs SPIsIMO 2nd Data to Write 8rd Data to Write 4th Data to Write SPISOMI 1st Read Data 2nd Read Data 3rd
18. AN3 at ADC3 are always 1 0V V with respect to 2 5V Table 1 5 13 bit VECANA ADIN Word Format viz bn bo w w be 9 4 9 DACA DAcz Daci GANi 3 21 Input Channel Selection Table 1 6 shows the relationships between the value of the input select bits and the input channels that are converted Table 1 6 Controls for Input Multiplexers and Sample Holds INPUT SELECT BITS 2 0 ANALOG SIGNAL CONNECTED TO ADCx HEX CODE BINARY CODE ADC ADC2 ADC3 Input Select 0 The synchronous sample and hold 5 5 samples AN3 only then ADC3 converts it on the signal HOLD1 Input Select 14 AX is sampled by the asynchronous sample and hold SHg with the signal HOLD2 ADC1 converts it on the signal HOLD1 BX is sampled by the asynchronous sample and hold 5 7 with the signal HOLD2 ADC2 converts it on the signal HOLD1 ANS is sampled by the synchronous sample and hold SHs then ADC3 converts it on the signal HOLD1 The signal HOLD2 must be low during the entire conversion If HOLD2 is high before a conversion starts ADC and ADC will not convert Input Select 24 A2 is sampled by the synchronous sample and hold SH4 ADC converts it on the signal HOLD1 B2 is sampled by the synchronous sample and hold SH3 converts it on the signal HOLD1 AN2 is sampled by the synchronous sample and hold SH5 ADC converts it on the signal HOLD1
19. C W 45 C W 22 222mW C 2778mW 1778mW 1444mW High K 2 PZT 3 5 C W 2 82 C W 35 461mW C 4433mW 2837mW 2305mW 1 The JEDEC Low K 1s board design used to derive this data was a 3 inch x 3 inch two layer board with 2 ounce copper traces on top of the board 2 The JEDEC High K 2s2p board design used to derive this data was a 3 inch x 3 inch multilayer board with 1 ounce internal power and ground planes and 2 ounce copper traces on the top and bottom of the board 4 ate Motor Control Front End with Simultaneous Sampling on INST E AS rs Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs www ti com ADS7869 SBAS253E MAY 2003 REVISED JULY 2006 1 5 ELECTRICAL CHARACTERISTICS Over recommended operating free air temperature range at 40 C to 85 C 5V BVpp 3 3V VREF internal 2 5V 16MHz fSAMPLE 1 MSPS unless otherwise noted ADS78691 PARAMETER CONDITION MN 1 wA UNIT Resduon TE Analog Input Full scale Voltage Differential See Gain Adjustment Input Capacitance Input Leakage Current Mag DC Accuracy No Missing Codes INL Integral Linearity Error DNL Differential Linearity Error Vos Bipolar Offset Error Synchronous Channels Vos Bipolar Offset Error AX and BX Channels Vos Bipolar Offset Match IU IV and IW Channels Vos Bipolar Offset Match A1 B1 A2 and B2 Channels Vos Bip
20. C to 85 C AVpp 5V BVpp 3V 5V PARAMETER ADCLK Period ADCLK HIGH or LOW Time Input Data Setup Time Input Data Hold Time Delay Tie fon ADULK ng BOA RG EE 1 rs Sampling Time C ewe Data OUT D11 MSB DN Data OUT D11 MSB 1 i gt Data OUT Data OUT Data OUT EXE ee XX tha Data IN Data Data IN D11 D10 D12 MSB om po LSB p12 LSB Figure 1 10 VECANA Access 26 i pna og Motor Control Front End with Simultaneous Sampling on INSTRUMENTS Seven S H Capacitors and Three 1MSPS 12 Bit fe E SBAS253E MAY 2003 REVISED JULY 2006 3 2 3 WINCLK Selection It is possible to apply a separate clock for the window comparators at the WINCLK pin 51 in VECANAO1 mode By using the pins SO pin 52 and S1 pin 53 as decoder inputs the window comparators can be supplied with the system clock an external clock supplied by the WINCLK and two divided external clocks see Table 1 7 Table 1 7 Window Comparator Clock 8 Clock to Window Comparators E External WINCLK clock 2 External WINGLK clock 4 The system clock provided by CLK pin 77 drives the window comparators in the other modes SPI and parallel modes The window comparator clock WINCLK must be synchronous with the system clock provided by CLK pin 77 The window comparators can be supplied with a 6MHz
21. Read Data 4th Read Data gt Figure 1 12 Continuous SPI Transfer Cycle 28 Analog Motor Control Front End with Simultaneous Sampling on 35 TEXAS 9 ET e Seven S H Capacitors and Three 1MSPS 12 Bit 12 xL E www ti com SBAS253E MAY 2003 REVISED JULY 2006 3 3 1 SPI Timing Characteristics Over recommended operating free air temperature range at 40 C to 85 C AVpp 5V BVpp 5V PARAMETER ww wm SPICLK Period SPICLK HIGH of LOW Tine a De Tie on SPSTE Fang SPOIR ATG ERE Delay Time from SPISTE Falling to SPISOMI not Tristate 52 E S arera OwpurDamDemyTme somom Sequential TansferDey 1 All input signals are specified with tR 5 10 to 90 of BVpp and timed from a voltage level of VjH 2 SPISTE i gt SPICLK 8 9 10 24 i 4 Command Bit Don t Address Address Data IN Data IN 5 015 MSB id 00 LSB Diu M da gt 1 Data OUT 14 Data OUT SPISOMI ER D15 MSB LSB 4 1 Figure 1 13 SPI Access 29 Analog Motor Control Front End with Simultaneous Sampling on Seven 5 Capacitors and Three MSPS 12 Bit 12 Channel ADCs WO Texas www ti com
22. SBAS253E MAY 2003 REVISED JULY 2006 3 4 Parallel Interface The Parallel Interface has the following major capabilities 1 Data words e Data path with a width of 16 bits is supported 2 Bus handshaking e Separate RD and WR style control signals e Separate R W and WE style control signals 3 Mapping e The ADS7869 appears as a memory mapped peripheral See Table 1 10 on page 37 and Table 1 11 on page 38 e Internal registers are directly mapped into consecutive locations in the external bus address space 3 441 Parallel Read and Write Control Reading from and writing to the ADS7869 is controlled by the chip select input CS pin 57 the write input WR pin 58 and the read input RD pin 59 There is a control bit for mode 11 which can be reset to activate a special compatibility mode See Mode 11 Bus Access DSP compatible mode section The read and write pins can be configured as a combined Read Write and Write enable depending on the needs of the host processor The mode pins MO and M1 determine the method by which the ADS7869 is accessed by the host see Table 1 9 Table 1 9 Host Parallel Port Operation FUNCTION OPERATION Read Write Signal 0 Data can be written to ADS7869 see WE signa 1 Data from ADS7869 is written to the Data Bus 0 Data Bus is read by ADS7869 at rising edge DET d 1 ADS7869 Write function is disabled Read Signal 0 Data from ADS7869 is written to the Data Bus 1 ADS7869 Read functi
23. TEXAS PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 29 Oct 2009 TAPE AND REEL BOX DIMENSIONS All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length mm Width Height mm ADS7869IPZTR TQFP PZT 100 1000 346 0 346 0 41 0 Pack Materials Page 2 MECHANICAL DATA MTQF012B OCTOBER 1994 REVISED DECEMBER 1996 PZT S PQFP G100 PLASTIC QUAD FLATPACK 0 13 NOM 14 2 50 e 12 00 TYP i 13 80 16 20 15 80 0 05 MIN Seating Plane 1 20 MAX 4073179 B 11 96 NOTES All linear dimensions in millimeters B This drawing is subject to change without notice C Falls within JEDEC MS 026 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1
24. and positioned at 90 electrical degrees to each other The sign comparators with typically 75mV hysteresis process the position sensor output differential signal This dramatically reduces the common mode noise which is present in motor control applications The digital output signal from the comparator is connected to the counter input Extra noise suppression is obtained with Schmitt trigger inputs The digital signals are carried through a programmable digital filter The filtered glitch free signals are processed by a state machine which increments or decrements the counters The counter values are then latched into corresponding registers by the synchronous or asynchronous hold signals HOLD1 and HOLD2 There is a counter module implemented for each pair of position sensor signals A1 B1 and A2 B2 These counters can count upwards or downwards depending on the direction of the position sensor signal that is the phase difference of the signals A1 and B1 respectively or A2 and B2 These counter values are stored in shadow registers when the ADC channels are sampled and held The four position sensor channels and the counter values are all sampled at the same time on the HOLD1 or HOLD2 signal With a 16MHz system clock the maximum data rate that the counters will operate at is 2MHz 52 i ana og Motor Control Front End with Simultaneous Sampling on INSTRUMENTS Seven S H Capacitors and Three 1MSPS 12 Bit i SBAS25
25. and timed from a voltage level of 2 2 With the DAV bit in the Control register 14 the DAV signal can have opposite polarity 3 Only applicable when the last data is read from the FIFO DAV 2 SPISTE 3 i gt 4 i DAV 1 Parallel mode 11 2 Parallel mode 10 and TMS320C54xx mode 3 SPI mode Figure 1 22 Timing of the DAV Signal 51 Analog Motor Control Front End with Simultaneous Sampling on 4 Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs TEXAS ADS7869 INSTRUMENTS SBAS253E MAY 2003 REVISED JULY 2006 3 8 Digital Counter Modules The interface of the ADS7869 for the analog position sensors has the following features Up to 16MHz operation frequency e Error safe state machine for fully four quadrant decoding e High noise immunity Differential signal inputs Analog input comparators with hysteresis Schmitt trigger digital inputs e Digital Noise Filter e 16 bit binary Up Down counters with over and under flow detection e Synchronous to the system clock e Asynchronous and synchronous latching of the counter values at the same time as the ADC values are sampled and held e Five shadow registers 16 Bit 16 Bit Digital Filter State Machine Binary Counters Registers FiltA1 FiltB1 Figure 1 23 Block Diagram of a Counter Module 3 8 1 Operation Analog position sensors have two signals on the output sine and cosine Both signals are differential
26. bit14 bit13 bit t1 bit 10 bit 5 15 0000 015 2 The 14 MSBs of the synchronous latched edge counters D1 0 2 LSBs of the synchronous latched edge counters The value is adjusted to the value of the CNTAx and CNTBx by a write access to these registers or a reset condition 9 o8 39 L9 The data only be read from the asynchronous latched registers ASEDGCNT1 ASEDGCNT2 see Table 1 19 Table 1 19 Asynchronous Latched Edge Count Register my p mo Ro m T T 9T bit2 bit bit 1 biz 15 015 0 The 16 bits of the asynchronous latched edge counters 3 6 8 Edge Period Register 1E and 22 There are two read only shadow registers for the two edge period registers The registers SYEDGPRD1 and SYEDGPRD2 synchronous edge period 1 in address 1 and synchronous edge period 2 in address 224 latch the values from the edge period registers when the synchronous hold signal HOLD1 is set to low The Edge Period Register is described in Table 1 20 Table 1 20 Edge Period Register me mv m mo j om 03 prs bir BTS bei T Bio Bit15 0 7 1 D15 0 The 16 bits of the synchronous latched edge period registers 43 Analog Motor Con
27. filtered FB2E Enable of digital filter input CNTB2 1 Input signal of CNTB2 will be filtered 0 Input signal of CNTB2 will not be filtered FA1E Enable of digital filter input CNTA1 1 Input signal of will be filtered 0 Input signal of CNTA1 will not be filtered FB1E Enable of digital filter input CNTB1 1 Input signal of CNTB1 will be filtered 0 Input signal of CNTB1 will not be filtered 42 i ana og Motor Control Front End with Simultaneous Sampling on INSTRUMENTS Seven S H Capacitors and Three 1MSPS 12 Bit fee E SBAS253E MAY 2003 REVISED JULY 2006 3 6 7 Edge Count Register 1 1D 20 and 21 There are four shadow registers for the two edge counters The registers SYEDGCNT1 and SYEDGCNT2 synchronous edge count 1 in address 1Dy and synchronous edge count 2 in address 21 latch the values from the edge counters when the synchronous hold signal HOLD1 is set to low Registers ASEDGCNT1 ASEDGCNT2 asynchronous edge count 1 in address 1Cy and asynchronous edge count 2 in address 20 latch the values from the edge counters when the asynchronous hold signal HOLD is set to low An initial value is given to the edge counter 1 EDGECNT1 by writing into the register SYEDGCNT1 An initial value is given to the edge counter 2 EDGECNT2 by writing into the register SYEDGCNT2 see Table 1 18 Table 1 18 Synchronous Latched Edge Count Register RWO EUM biti5
28. gt 46 2 z g 5 344 gt 42 40 40 25 85 Temperature C ADC OFFSET ERROR vs TEMPERATURE 3 0 2 8 e 9 2 6 2 E 2 4 2 2 2 0 40 25 85 Temperature C ADC GAIN ERROR AT 1V V GAIN vs TEMPERATURE 0 07 0 06 x 5 0 05 S s 9 0 04 0 03 40 25 85 Temperature C REFERENCE VOLTAGE vs TEMPERATURE 2 500 2 498 2 496 2 494 2 492 2 490 40 25 85 Temperature C ADC OFFSET MATCH vs TEMPERATURE FOR ALL CHANNELS 6 0 55 a o 50 3 45 4 0 40 25 85 Temperature C ADC GAIN ERROR AT 5V V GAIN vs TEMPERATURE 4 3 S 5 2 5 1 0 40 25 85 Temperature C 11 Analog Motor Control Front End with Simultaneous Sampling on Seven 5 Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs WO Texas www ti com SBAS253E MAY 2003 REVISED JULY 2006 TYPICAL CHARACTERISTICS Continued At TA 25 C AVpp 5V BVpp 3 3V internal 2 5V 16MHz fSAMPLE 1 MSPS unless otherwise noted ADC DIFFERENTIAL LINEARITY ADC DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE vs CODE 0 5 0 5 5 m ao s 2 E a 0 5 0 5 40 25 85 0 1024 2048 3072 4095 Temperature C Code ADC INTEGRAL LINEARITY ERROR ADC INTEGRAL LINEARITY ERROR vs TEMPERATURE vs CODE 2 Ma
29. important to drive the inputs with low impedance The lower voltage of the differential input should remain within the range of 0 to AVpp 1 8V Analog To Digital Converter The ADS7869 includes three SAR type 1MSPS 12 bit ADCs and three pairs of S H capacitors which are each connected to ADC and ADC A single S H capacitor is connected to ADC3 Gain and offset adjustments are added to each ADC See Figure 1 2 on page 15 HOLD1 HOLD2 The analog inputs are held when the HOLDx signals go low The charges of the synchronous sample and holds 5 4 5 are frozen on the falling edge of HOLD1 The setup time of HOLD1 against the rising edge of the system clock is typically 25ns The conversion will automatically start on the next rising edge of the clock The S Hs are switched back into the sample mode when the conversion is finished 12 clock cycles later This point of time is indicated by DAV See Figure 1 10 on page 26 HOLD1 must go high at the latest at the 13th falling clock after conversion start The asynchronous sample and holds S Hg 7 are triggered by the active low HOLD2 signal The setup time of HOLD2 against the falling edge of HOLD1 is Ons see Figure 1 10 The conversion of these S H circuits is initiated when they are selected through the digital interface and the HOLD1 signal goes low The inputs are connected back to the S H capacitor when the HOLD2 signal goes high HOLD2 needs to be low during the wh
30. input voltage remains within this range then the output of the window comparator is 1 If the voltage is outside this range then the output is set to 0 The window comparator has a hysteresis that is turned on when the output is 0 The comparator outputs switch back to 1 when the input voltage is within the range of DAIN 60mV See Figure 1 9 The voltage at DAIN needs to be in a range of 0 5V to 2 5V The window comparator has a switched capacitor circuitry similar to the ADC architecture but different from other window comparators This design dramatically increases the accuracy due to the additional accuracy a proper front end of the input signal is required See the Window Comparator Inputs section Comparator Output Figure 1 9 Typical Transfer Function of a Window Comparator Two clock cycles are used to sample the inputs The next two clock cycles are used to test the lower and the upper voltage limit Every four clock cycles or every 250ns with a 16MHz clock the output of the window comparator is updated In a worst case scenario it takes six clock cycles for the window comparator to detect a current limit The window comparators need a continuous clock to operate properly In motor control applications the window comparators are used to monitor the main currents for failures 21 Analog Motor Control Front End with Simultaneous Sampling on Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs
31. otherwise noted 1 ADS78691 UNIT Supply voltage AVpp to AGND 0 3 to 6 V Supply voltage BVpp to BGND 0 3 to 6 V Analog input voltage with respect to AGND AGND 0 3 to AVpp 0 3 V Reference input voltage with respect to AGND AGND 0 3 to AVpp 0 3 V Digital input voltage with respect to BGND BGND 0 3 to BVpp 0 3 V Ground voltage difference AGND to BGND 0 3 V Input current to any pin except supply 10 to 10 mA Operating virtual junction temperature range Ty 40 to 150 C Operating free air temperature range TA 40 to 85 C Storage temperature range TSTG 65 to 150 C Lead temperature 1 6mm 1 16 inch from case for 10 seconds 260 C 1 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability 1 3 RECOMMENDED OPERATING CONDITIONS Analog Inputs also see Fully Differential Analog Inputs section Operating junction temperature range TJ 40 85 1 4 PACKAGE DISSIPATION RATINGS DERATING FACTOR lt 25 C TA 70 C 85 C BOARD PACKAGE ReJc RoJA ABOVE 25 POWER RATING POWER RATING POWER RATING Low K 1 PZT 3 5
32. to AVpp 1 8V On every comparator the output is delayed to the input voltage This delay is dependent on the overdrive of the comparator inputs The overdrive is the input voltage Vij minus one half of the hysteresis If the differential input voltage of the position sensor sign comparator is switching from 40mV to 40mV step function 2 5mV overdrive then the delay time of the output is typically 100ns The delay is reduced to typically 25ns if the comparator is switching between 100mV and 100mV 72 5mV overdrive For the delay times as a function of step size with different overdrives see Figure 1 7 and Figure 1 8 25 T gt 9 0 2 5 12 5 22 5 32 5 42 5 52 5 62 5 72 5 82 5 92 5 102 5 112 5 Overdrive mV Figure 1 7 Position Sensor Comparator Overdrive Delay Time ns 0 5 10 15 20 25 30 35 40 45 50 55 60 65 Overdrive mV Figure 1 8 Current Sign Comparator Overdrive 20 2 4 TEXA INSTRUMENTS at Motor Control Front End with Simultaneous Sampling on Seven S H Capacitors and Three 1MSPS 12 Bit www ti com AD 7869 SBAS253E MAY 2003 REVISED JULY 2006 Window Comparators The window comparators test if the input voltage is within a certain range this range is voltage applied to DAIN pin 30 If the differential
33. with Simultaneous Sampling on Seven S H Capacitors and Three 1 5 5 12 Bit 12 Channel ADCs ADS7869 SBAS253E MAY 2003 REVISED JULY 2006 TYPICAL CHARACTERISTICS Continued 3 TEXAS INSTRUMENTS www ti com At TA 25 C AVpp 5V BVpp 3 3V VREF internal 2 5V 16 2 fSAMPLE 1 MSPS unless otherwise noted ENCODER COMPARATOR HYSTERESIS vs TEMPERATURE 75 73 gt E 72 E o v 69 67 65 40 25 85 Temperature C SIGN COMPARATOR HYSTERESIS vs TEMPERATURE 11 0 10 8 e E 106 2 o 10 4 10 2 10 0 40 25 85 Temperature C WINDOW COMPARATOR HYSTERESIS vs TEMPERATURE 74 72 gt pcc dem T 2 70 2 68 66 40 25 85 Temperature C ENCODER COMPARATOR OFFSET vs TEMPERATURE 4 3 8 O 2 1 0 40 25 85 Temperature C SIGN COMPARATOR OFFSET vs TEMPERATURE 3 0 2 5 _ 2 0 gt 15 1 0 0 5 0 40 25 85 Temperature C WINDOW COMPARATOR OFFSET vs TEMPERATURE 7 8 vw 9 e 10 DAIN 2 4V 25 Temperature C 14 ona og Motor Control Front End with Simultaneous Sampling on Texas Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs INSTRUMENTS ADS7869 SBAS253E MAY 2003 REVISED JULY 2006 1 11 FUNCTIONAL BLOCK DIAGRAM
34. 3E MAY 2003 REVISED JULY 2006 3 8 2 Digital Noise Filter A digital noise filter rejects noise on the incoming quadrature signal The digital noise filter rejects large short duration noise spikes false counts triggered by noise or spikes are also significantly suppressed See Figure 1 24 FiltA1 FiltB1 Figure 1 24 Digital Noise Filter Block Diagram The input signals Cntyy are sampled on the rising clock edge Before the signals are passed to the state machine the signals must be stable for a minimum of three consecutive rising clock edges Pulses shorter than two clock periods are rejected glitches between rising clock edges are also ignored See Figure 1 25 53 Analog Motor Control Front End with Simultaneous Sampling on 4 Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs TEXAS INSTRUMENTS ADS7869 www ti com SBAS253E MAY 2003 REVISED JULY 2006 3 8 2 1 Filtered Timing Characteristics 1 Over recommended operating free air temperature range at 40 C to 85 C AVpp 5V BVpp 3V 5V PARAMETER SYMBOL Ww E wo ws o 1 2 Figure 1 25 Timing Diagram of the Counter Signals with the Digital Noise Filter Enabled 54 Anaiog Motor Control Front End with Simultaneous Sampling on x TEXAS Seven S H Capacitors and Three 1MSPS 12 Bit E www ti com SBAS253E MAY 2003 REVISED JUL
35. 69 is used for the next conversion cycle while the ADCs are converting and transmitting their serial digital data for one conversion cycle The 13 bit word is supplied to ADIN pin 67 and is stored in the buffered Input Setup Register Configuration parameters are e DAC output voltage e Programmable gain input voltage range e Input multiplexer and sample and hold selection The DAC Input portion of the ADIN word bits DAC 7 0 determines the value of the DAC output voltage see Table 1 5 The 8 bit DAC has 256 possible output steps from OV to 2 490V The value of 1LSB is 9 76mV see Table 1 3 for input output relationships Table 1 3 to Table 1 6 show information regarding these parameters Table 1 3 DAC Input Output Relationships DAC Input Code Analog Output 0000 00005 0000 00018 1 450 Table 1 4 VECANA Gain Select Information Gain Select Bits Gain Setting Input Voltage Range 5 0VIV 25VN TOVN 24 pna og Motor Control Front End with Simultaneous Sampling on INSTRUMENTS Seven S H Capacitors and Three 1MSPS 12 Bit 12 uL 15 SBAS253E MAY 2003 REVISED JULY 2006 The Gain Select portion bits GAIN 1 0 determines the programmable gain of the ADIN word see Table 1 5 The gain for all three ADCs is set by one gain input parameter The gain values and allowable full scale inputs are shown in Table 1 4 The gain setting and input voltage range for the channels AN1 AN2 and
36. ADS7869 Analog Motor Control Front End with Simultaneous Sampling on Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs Data Manual Literature Number SBAS253E May 2003 Revised July 2006 35 TEXAS INSTRUMENTS IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warr
37. Channel ADCs INSTRUMENTS ADS7869 SBAS253E MAY 2003 REVISED JULY 2006 1 8 BASIC CIRCUIT CONFIGURATION Encoder Counter1 5V Analog Supply Inputs Convert Start Asynchronous Hold Asynchronous Reset O 5V Analog Supply Mode Select O 2 7V to 5 5V Digital Supply 10uF e 0 1HF System Clock Data Available 1 REFOUT AGND 45V Analog Supply AVpp AXp n AN3p n Data Bus 2 Read SGND ADS7869 Write AN1p n Chip Select 5V IWp n Address Bus Analog Supply AVpp 0O1MF BXp n AGND IVp n B1p n Comparator Outputs gt Interrupt 3 Differential 0 1uF Inputs to Comparators Encoder Counter2 Inputs 4 2 7V to 5 5V 5V Digital Supply Analog Supply Analog Motor Control Front End with Simultaneous Sampling on 4 RA S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs 1 5 nrs AD 7869 www ti com SBAS253E MAY 2003 REVISED JULY 2006 1 9 10 TYPICAL APPLICATION CIRCUIT DC Link Voltage IGBTs C o Analog Input Over Current 7 S amp H Comparato
38. DCs WO Texas www ti com SBAS253E MAY 2003 REVISED JULY 2006 1 5 ELECTRICAL CHARACTERISTICS continued Over recommended operating free air temperature range at 40 C to 85 C AVpp 5V BVpp 3 3V VREF internal 2 5V 16MHz fSAMPLE 1 MSPS unless otherwise noted ADS78691 PARAMETER CONDITION 1 UNIT Digital Inputs 3 Logic Family LVCMOS VIH High Level Input Voltage BVpp 3 6V Vi_ Low Level Input Voltage BVpp 2 7V lin Input Current Vi BVpp to BGND Cj Input Capacitance Digital Outputs 3 Logic Family LVCMOS VOH High Level Output Voltage BVpp 2 7V 1004A VoL Low Level Output Voltage BVpp 2 7V lot 100uA loz High Impedance State Output Current Vi BVpp to BAND Co Output Capacitance Load Capacitance Power Supply Analog Supply Voltage BVpp Buffer I O Supply Voltage Alpp Analog Supply Current Buffer Supply Voltage Power Dissipation Reference Output VREF Reference Output Voltage 40 C gt t gt 85 C Reference Output Voltage at 25 C Reference Voltage Drift PSRR Power Supply Rejection Ratio louT Output Current DC Current Short Circuit Current toN Turn On Setting Time Reference Input ViN Reference Input Voltage Input Resistance Input Capacitance Digital to Analog Converter Resolution Output Range INL Integral Linearity Error DNL Differential Linearity Error Offse
39. EFOUT pin in able to reduce noise It is recommended that a 0 1uF capacitor be connected between the REFOUT pin 96 and the SGND pin 13 The Signal ground SGND is used internally as a negative reference The reference voltage is considered a differential voltage between this ground and REFOUT Normally the REFOUT and REFIN pins are both shorted The internal reference provides an excellent temperature drift typically 20ppm an initial accuracy of 2 5V 20mV at 25 C If this does not provide the required accuracy for an application then an external reference can be connected to the REFIN pin Grounding Optimal test results were achieved with a solid ground plane linearity offset and noise performance each showed improvement During PCB layout care should be taken that the return currents do not cross any sensitive areas or signals Digital signals that interface with the ADS7869 are referenced to the solid ground plane ESD protection diodes inside the ADS7869 start conducting if the grounds are separated and the digital inputs go below 0 3V this includes short glitches Current will flow through the substrate of the ADS7869 and will disturb the analog performance Supply The ADS7869 has two separate supplies BVpp pins 48 and 78 and AVpp pins 8 18 28 85 and 98 BVpp is used as a digital pad supply only and is in the range of 2 7V to 5 5V This allows the ADS7869 to interface with all state of the art processors an
40. Interface The VECANAO1 mode of the ADS7869 interface acts exactly like the original VECANAO interface This mode was added to the ADS7869 for backward compatibility purposes The VECANAO interface is a proprietary serial interface with one serial input and three serial outputs Sampling and conversion are controlled with the HOLD1 and CLK inputs The ADS7869 is designed to operate with an external clock supplied to the CLK input This allows the conversion to be synchronous with the system clock thus reducing transient noise effects The DAV signal indicates when a conversion is taking place with a low level pulse The DAV signal is equivalent to the ADBUSY signal in the VECANAO 1 The typical clock frequency for the specified accuracy is 16MHz This results in a complete conversion cycle S H acquisition and analog to digital A D conversion of 1us It is possible to stop the clock after 14 clock cycles and start it again when the next conversion starts after HOLD1 goes low see the WINCLK Selection section When power is applied to the ADS7869 one conversion cycle is required for initialization before valid digital data is transmitted on the second cycle The first conversion after power is applied is performed with indeterminate configuration values in the Input Setup Register The second conversion uses those values to perform proper conversions and to output valid digital data from each of the ADCs The setup word received by the ADS78
41. O is or was full and remains set until the Interrupt Register is read independent of whether the FIFO is full or not The FF bit FIFO full indicates whether the FIFO is full or not The FFF bit is cleared when the Interrupt Register is read The FIFO full interrupt is enabled when the bit FFE or FIFO full enable is set The FEF bit FIFO empty flag will be set when the FIFO is or was empty and remains set until the Interrupt Register is read independent of whether the FIFO is empty or not The FE bit FIFO empty indicates if the FIFO is empty or not The bit FEF is cleared when the Interrupt Register is read The FIFO empty interrupt is enabled when the FEE bit FIFO empty enable is set For more information about the Interrupt pin see the nterrupt section Table 1 24 describes the Interrupt Register Table 1 24 Interrupt Register m T me pw EO2E Edge counter 2 EDGECNT2 over or under flow interrupt enable bit 1 Interrupt enable 0 Interrupt disable 2 Time counter 2 TIMECOUNT2 over under flow interrupt enable bit 1 Interrupt enable 0 Interrupt disable Edge counter 1 EDGECNT1 over or under flow interrupt enable bit 1 Interrupt enable 0 Interrupt disable TO1E Time counter 1 TIMECOUNT1 over or under flow interrupt enable bit 1 Interrupt enable 0 Interrupt disable EO2F Edge counter 2 EDGECNT2 over or under flow flag 1 EDGECNT2 over or under flow occurred 0
42. S H Capacitors and Three 1MSPS 12 Bit 12 Channel AD Cs www ti com SBAS253E MAY 2003 REVISED JULY 2006 3 4 8 Mode 11 Bus Access Standard Mode When M1 1 and MO 1 mode 11 the host port uses WR pin 58 and RD pin 59 for independent write and read access to the ADS7869 The current cycle is processed only when the CS pin 57 input of the ADS7869 is an active low Bit 0 of the PARALLEL register Address 274 must have a reset value of 1 to use the standard mode In Mode 11 operation RD indicates to the ADS7869 that the host processor has requested a data transfer see Figure 1 16 The ADS7869 outputs data to the host The address can be changed within a CS low cycle and more than one data can be read To configure the registers in the ADS7869 the host issues a WR signal to indicate that valid data is available on the bus With the rising edge of the WR the data is latched into the ADS7869 see Figure 1 17 The address for the ADS7869 must be valid before the write operation takes place The CS signal can stay low between two consecutive writes 3 4 3 1 Read Timing Characteristics 1 Over recommended operating free air temperature range at 40 C to 85 C AVpp 5V BVpp 3V 5V UNIT ns ns ns ns PARAMETER SYMBOL Delay time from CS LOW to output data not in tri state mode i 1 1 Access time from address valid to output data valid tat Delay time from address not valid to output data not valid De
43. Sign of Phase U Current V COMP 43 W COMP 44 U ILIM 45 6 7 Other Analog Signals AN x p 15 12 10 Analog In Auxiliary Analog Input Channel x Positive Input AN x n 14 11 9 Analog In Auxiliary Analog Input Channel x Negative Input REFIN 97 Reference Voltage Input Pin REFOUT 96 Reference Voltage Output Pin NC 84 92 93 94 m No connection should be left open DIGITAL INTERFACE SIGNALS ADDR x 56 51 Address Decode 1 DATA xx 75 60 Bidirectional 3 state Data Bus 1 S 5 Active Low Chip Select Signal 1 Active Low Read Signal 1 V ILIM 4 W_ILIM 4 5 5 Digital In Active Low Write Signal 1 7 Digital In System Clock 7 9 8 7 9 gt 4 Digital Out Active High Interrupt Output 79 Digital In Active Low Reset Input 81 80 Digital In Mode Select Pins 1 Digital Out Data Available Signal HOLD1 87 Digital In Active Low Convert Start and Synchronous Hold Signal for Sample and Hold Amplifiers HOLD2 86 Active Low Asynchronous Hold Signal for Sample and Hold Amplifiers POWER SUPPLY AVDD 8 18 28 85 98 Power Analog Power Supply BVpp 48 78 Interface Power Supply AGND 5 21 37 82 95 Analog Ground BGND 50 76 Interface Ground SGND 13 fF Signal Ground 1 See Digital section for detailed information about the different modes 4 pna og Motor Control Front End with Simultaneous Sampling on TEXAS Seven S H Capacitors and Three 1MSPS 12 Bit 12
44. Texas INSTRUMENTS A DS7869 www ti com SBAS253E MAY 2003 REVISED JULY 2006 2 5 2 6 2 7 2 8 22 8 Bit Digital to Analog Converter A voltage between 0 5V to 2 5V is required at DAIN pin 30 to set the range of the window comparators this can be accomplished with the 8 bit DAC The DAC value is programmed via the digital interface Input code 004 corresponds to a DAC output voltage of OV The full scale value is at 2 49V internal reference minus 1LSB The impedance of the output is typically 10kQ the output impedance is independent of the output voltage The DAC output is connected to DAOUT 29 The settling time ts is dependent on the external capacitance on this and can be calculated to ts 10kQ Ce n 1 In 2 2 In this equation n is equal to 8 the resolution of the DAC The output impedance also limits the output current This current should not exceed 0 5uA 0 5 10 5mV DAOUT and DAIN can be shorted A capacitor typically 0 1uF can be used to low pass the DAC output however this low pass configuration is not required Internal Reference The internal reference REFOUT pin 96 provides the 2 5V required for the reference input of the ADCs at REFIN pin 97 An internal buffer with a high impedance output drives the reference output pin This internal buffer is optimized to reject glitches at the reference pin Any capacitor can be connected to the R
45. UC Control bit phase U current sign comparator 1 Comparator output U_COMP set HIGH 0 Comparator output U COMP set LOW VC Control bit phase V current sign comparator 1 Comparator output V COMP set HIGH 0 Comparator output V COMP set LOW WC Control bit phase W current sign comparator 1 Comparator output W_COMP set HIGH 0 Comparator output W_COMP set HIGH UI Control bit phase U current window comparator 1 Comparator output U_ILIM set HIGH 0 Comparator output U_ILIM set LOW VI Control bit phase V current window comparator 1 Comparator output V_ILIM set HIGH 0 Comparator output V_ILIM set LOW WI Control bit phase W current window comparator 1 Comparator output W_ILIM set HIGH 0 Comparator output W_ILIM set LOW 45 Analog Motor Control Front End with Simultaneous Sampling on 4 Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs TEXAS ADS7869 INSTRUMENTS SBAS253E MAY 2003 REVISED JULY 2006 3 6 12 Interrupt Register 26 The Interrupt Register in address 264 contains the interrupt source and interrupt control bits The bits xOxF are set when a particular counter had an over or under flow The bits remain set until the Interrupt Register is read this is independent of whether the counter over or under flow states remain or not The counter over or under flow interrupt is enabled when the appropriate xOxE bits are set The FFF bit FIFO full flag will be set when the FIF
46. Y 2006 3 8 2 2 Unfiltered Timing Characteristics Over recommended operating free air temperature range at 40 C to 85 C AVpp 5V BVpp 3V 5V WA T Ur foe Cwmermpursgna CWTATorONTBT Paved Owe ns Counter input signal CNTA1 or CNTB1 HIGH or LOW time Delay between CNTA1 or 1 signal any combination 1 All input signals are specified with tR 5ns 10 to 90 of BVpp and timed from a voltage level of VjH 2 PARAMETER SYMBOL CLK Period Figure 1 26 Timing Diagram of the Counter Signals with the Digital Noise Filter Disabled 55 Analog Motor Control Front End with Simultaneous Sampling on S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs 5 AD 7869 www ti com SBAS253E MAY 2003 REVISED JULY 2006 3 8 8 Binary Counters and Registers The complete up down counter includes two 16 bit counters and five 16 bit shadow registers The first counter is a 16 bit up down counter which counts upwards or downwards on the EDGE input signal as a function of the U D signal This is the coarse angle counter and it is called EDGECNT For the fine angle computation the second 16 bit counter TIMECOUNT is implemented This counter increments with the system clock and resets when the EDGE signal occurs The TIMECOUNT counter cannot be decremented The system is shown in Figure 1
47. acitors and Three 1MSPS 12 Bit fee i SBAS253E MAY 2003 REVISED JULY 2006 3 4 4 Mode 11 Bus Access 5320 54 DSP Family Compatible Mode In the TMS320c54xx DSP family compatible mode M1 1 and MO 1 the host port uses CS pin 57 together with WR pin 57 as an R W for independent read and write access to the ADS7869 Bit 0 of the PARALLEL register address 274 must have a value of 0 to use this compatible mode In this mode CS together with the R W which remains high indicates to the ADS7869 that the host processor has requested a read data transfer see Figure 1 18 The ADS7869 will output data to the host as long as the CS is an active low To configure the registers in the ADS7869 the host puts the R W signal to low to indicate that valid data is available on the bus With the rising edge of the CS the data is latched into the ADS7869 see Figure 1 19 The address for the ADS7869 must be valid before the CS is set to low Before using this mode the register bit 0 at address 27 must be reset The reset can be performed with a TMS320C54xx DSP write operation with the original mode 11 because the write access is similar to the write access of mode 11 See Mode 11 Bus Access standard mode section This mode can perform read operations after bit 0 is reset as mentioned above 3 4 4 1 Read Timing Characteristics Over recommended operating free air temperature range at 40 C to 85 C AVpp 5V BVpp
48. alog inputs The value of the SYEDGTIME Register represents the time between the last EDGE signal and the synchronous hold signal HOLD1 The EDGECNT counter value is stored into a shadow register ASEDGCNT on the asynchronous sample signal HOLD2 The shadow registers SYEDGCNT ASEDGCNT SYEDGPRD and SYEDGTIME can be read through the register map The counter EDGECNT can be written through the address of the SYEDGCNT Register in the register map The 14 MSBs of the written data are stored in the EDGECNT register The two LSBs are determined from the inputs FiltA1 and FiltB1 see the Edge Count Register section This is to prevent inconsistency between the EDGECNT counters and the ADC data of the position sensor input signals FiltA1 FiltB1 EDGE SYEDGCNT HOLD2 ASEDGCNT EPNCIk TIMECOUNT EDGEPRD EPNCIk EPNCIk SYEDGPRD SYEDGTIME Figure 1 28 Detail Counter Timing Diagram 57 Analog Motor Control Front End with Simultaneous Sampling on 4 Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs TEXAS INSTRUMENTS A DS7869 www ti com SBAS253E MAY 2003 REVISED JULY 2006 3 9 Interrupt The interrupt can have several sources e FIFO full status e FIFO empty status e Two TIMECOUNT over or under flows e Two EDGECOUNT over or under flows 3 10 These s
49. ant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from to use such products or services or a warranty or endorsem*nt thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice is not responsible or liable for any such statements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applicatio
50. ap econ pared 2 4 Window Comparators enda pred ded red Aud 2 5 8 Bit Digital to Analog Converter 2 6 Internal Reference i i ssec ess edd etr se ee eroe qoa drm o dox tet dcn A d 2 7 eicere 2 8 SE UELUT Analog Motor Control Front End with Simultaneous Sampling on Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs Texas ADS7869 INSTRUMENTS www ti com SBAS253E MAY 2003 REVISED JULY 2006 3 Digital 5 nein lie ee 3 1 ace 3 2 VECANA dug RR 3 2 1 Input Channel Selection 3 2 2 VECANA Timing Characteristics 3 2 3 WINGLK SelectiOri 1r et me dias Re Rem Rm eR cda 3 3 Serial Peripheral Interface SPI 3 8 1 SPI Timing Characteristics 3 4 Parallel Interace sd wees ede RE dee REN PP PE PRU CK 3 4 1 Parallel Read and Write Control 3 4 2 Mode 10 B us ACCOSS ciii ossis mre bu 4r bended 3 4 3 Mode 11 Bus Access Standard Mode
51. arties has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 1 ip TEXAS PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 29 Oct 2009 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS Reel Diameter Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness v Overall width of the carrier tape Y Pitch between successive cavity centers t Reel Width W1 QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes User Direction of Feed All dimensions are nominal Device Package Pins SPQ Reel Reel AO KO P1 1 Drawing Diameter Width mm mm mm mm mm Quadrant mm mm ADS7869IPZTR TQFP PZT 100 1000 330 0 24 4 17 0 17 0 1 5 20 0 24 0 Q2 Pack Materials Page 1 ip
52. ch is selected with the gain adjustment It is important that the voltage to all inputs does not exceed more than 0 3V above the analog supply or 0 3V below the ground There is no DC current flow through the inputs Current is only necessary when recharging the sample and hold capacitors Cs TEXAS INSTRUMENTS at Motor Control Front End with Simultaneous Sampling on Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs www ti com ADS7869 SBAS253E MAY 2003 REVISED JULY 2006 2 1 2 Window Comparator Inputs 2 2 2 2 1 A sampling architecture was selected for the window comparators The sampling time is two clock cycles with a minimum see Equation 1 of 125ns The necessary accuracy is 10mV see 8 bit DAC section with a 5V input range The required bandwidth of the driving amplifier is 8 8MHz see Equation 1 The OPAx354 from Texas Instruments is recommended The input circuit of the window comparator is similar to the ADC inputs The only difference is that the sampling capacitors are reduced to 2 5pF See Figure 1 4 Figure 1 4 Equivalent Input Circuit of the Window Comparators Sign Comparator Inputs Four sign comparators are connected to the ADC inputs A1 B1 A2 and B2 three of the sign comparators are wired to the window comparator inputs C V C W C The sample capacitors of the ADCs and the window comparators could produce voltage glitches therefore it is
53. clock when the system runs with a 15MHz clock In order to provide the window comparators with a maximum of ius detection time a minimum clock of 6MHz must be supplied See the Window Comparator section It is necessary to operate the window comparators with a continuous clock 3 3 Serial Peripheral Interface SPI The SPI runs fully asynchronous to the rest of the system The four signals of the SPI are SPICLK SPISIMO SPISOMI and SPISTE The maximum speed of the SPI is 25MHz When the select signal SPISTE is HIGH the entire SPI except the address and the data registers is in reset state The SPI clock SPICLK and the serial data input SPISIMO are disabled when SPISTE is HIGH The incoming data is strobed by the SPI on the falling edge of the SPICLK Outgoing data is put on the output SPISOMI on the rising edge of the SPICLK see Figure 1 11 For a transmission of one 16 bit data word 24 bits are required The first incoming bit to the ADS7869 determines if the whole transmission is a read or a write operation A 1 means a read and a 0 means write operation There are seven address bits but only the six LSBs are used Then the 16 data bits are transmitted or received see Table 1 8 SPISOMI Figure 1 11 One SPI Transfer Cycle Table 1 8 SPI Write 24 bit Word Format 27 Analog Motor Control Front End with Simultaneous Sampling on S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs TExas rs
54. d The read pointer always shows the location that contains the last read data The write pointer indicates the location that contains the last written sample The converted values are written in a predefined sequence to the circular buffer beginning with ADC and ending with ADC3 The channel number is stored with the ADC data The data of the FIFO is read through the FIFO register at address 00 its format is presented in Table 1 27 The table shows that the channel information for the converted channel data is continually maintained The address 00 in the register map shows only the data to which the read pointer is directed The FIFO generates the DAV signal see Figure 1 22 on page 51 In VECANA mode this signal is low it indicates that the ADS7869 is converting data see Figure 1 10 on page 26 In the other modes the DAV indicates that data in the FIFO is available The DAV signal can be configured as either a positive or negative signal see the Control Register section Table 1 27 FIFO 16 bit Data Read Format ADDRESS jer bM Dto B9 DS 0 value channel IU included offset and gain compensation 00 9 9 00 0 1 value channel 1 included offset and gain compensation ahr 8 9 10a sane rs aa 00 0 t 1 channel We included offset and gain compensation 00 1 o 0 4002 value channel BY included ofset and
55. d controllers BVpp should be filtered in order to limit the noise energy from the external digital circuitry to the ADS7869 The current through BVpp is far below 5mA depending on the external load 100 to 1000 resistor be placed between the external digital circuitry and the ADS7869 Bypass capacitors two 0 1 and one 10uF should be placed between the two BVpp pins and the ground plane AVpp supplies the internal circuitry and can vary from 4 5 to 5 5V It is not possible to use a passive filter between the digital board supply of the application and the AVpp pins because the supply current of the ADS7869 is typically 45mA In order to generate the analog supply voltage for the ADS7869 and the necessary analog front end a linear regulator 7805 family is recommended Bypass capacitors of 0 1uF should be placed between all AVpp pins and the ground plane Bypass capacitors of 10uF should be placed between two AVpp pins and the ground plane 4 pna og Motor Control Front End with Simultaneous Sampling on rs Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs www ti com ADS7869 SBAS253E MAY 2003 REVISED JULY 2006 3 Digital Section 31 Introduction The ADS7869 can interface with a DSP or uC in four different ways The M1 and MO pins determine in which mode the ADS7869 will communicate see Table 1 1 It can be connected as a standard VECANAO 1 interface as an SPI or as two different parallel interfaces
56. e times To distinguish between the channels the first data is unchanged to simulate ADC the second data is inverted to simulate ADC and the six LSBs of the third data are inverted to simulate ADC3 While the FIFO test is enabled a total of three data words will be stored in the FIFO with one write instruction In order to fill the entire FIFO register with test data 10 writes must be performed The test data is written into the FIFO only when the four enable bits have the value Ay This register should not be used in normal operation The format of the output word is shown in Table 1 22 Table 1 22 FIFO Test Register nwo ef E3 0 Input channel address bits 0000 Disable FIFO test 1001 Disable FIFO test 1010 Enable FIFO test write procedure 1011 Disable FIFO test 1111 Disable FIFO test 11 0 11 0 The input data that will be written into the FIFO registers In FIFO test mode the four channel bits are copied from Bit 11 of the written data 44 at Motor Control Front End with Simultaneous Sampling on Texas Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs INSTRUMENTS ADS7869 SBAS253E MAY 2003 REVISED JULY 2006 3 6 11 Comparator Test Register 25 The purpose of the Comparator Test Register in address 254 is to apply a defined pattern to the comparator output pins This feature is for testing algorithms in the DSP or testing the hardware controlled by the co
57. ead 12 bit gain DAC value Channel A2 read 12 bit gain DAC value Channel IV read 12 bit gain DAC value Channel B1 read 12 bit gain DAC value Channel B2 read 12 bit gain DAC value Channel IW read 12 bit gain DAC value Channel AN1 read 12 bit gain DAC value Channel AN2 read 12 bit gain DAC value Channel AN3 read 12 bit gain DAC value Channel AX read 12 bit gain DAC value Channel BX read 12 bit gain DAC value 194 Over read 8 bit window DAC value INPUT 1By Read counter control and status Read counter control and status register 1Cy Counter 1 read 16 bit value in ASEDGCNT1 rogister Teunie read 16 bit value in SYEDGPRD1 Counter 1 read 16 bitvalueinSYEDGPRD1 register 1Fy EE a a a a a a a aeae aeaaeae 1 read 16 bit value in SYEDGTIME1 register 204 Counter 2 read 16 bit value in ASEDGCNT2 register Counter 2 read 16 bit value in SYEDGCNT2 register 224 Counter 2 read 16 bit value in SYEDGPRD2 register 23H Counter 2 read 16 bit value in SYEDGTIME2 register 24 Read 16 bit value FIFO_TEST register Testei O O SOSEA Reante Tegs 000 O 264 Read INTERRUPT register b p b jp p fp fpe f e ri Read 0000H x Unused read 0000p 1 MSB is copied to upper bits to achieve 16 bit two s complement values 2 The lower 10 bits are the comparator outputs 3 The MSB of the 8 bit DAC is copied in the upper 8 bits oj o m r cr o m 1 D
58. ed The capacitor is then loaded to an initial voltage that is equal to the reference at the ADC which is selected with the gain adjustment The voltage of the input pin is usually different from the voltage of the sample capacitor when the input switch closes The sample capacitor needs to be recharged to the 12 bit accuracy one half of a least significant bit LSB within an acquisition time of at least 200ns The minimum 3dB bandwidth of the driving operational amplifier can be calculated to In 2 n 1 2 taa 1 ES where n is equal to 12 the resolution of the ADC in the case of the ADS7869 When taq 200ns the minimum bandwidth of the driving amplifier is 7MHz The bandwidth can be relaxed if the acquisition time is increased by the application The OPA364 from Texas Instruments is recommended besides the necessary bandwidth it provides a low offset in a small package at a low price The phase margin of the driving operational amplifier is usually reduced by the sampling capacitor of the ADC A resistor between the capacitor and the amplifier reduces this effect therefore an internal 3000 resistor Rser is in series with the switch The resistance of the closed switch Rsw is approximately 800 See Figure 1 3 Figure 1 3 Equivalent Input Circuit to the ADCs The differential input range positive minus negative input of the ADC is REF_ADC the reference of the converter whi
59. i nies Bhan wheal ended hated Ra ae eae aise 1 7 Pin FONCIONS 222 45 ee esse eer RR de E 1 8 Basic Circuit 1 9 Typical Application Circuit RII Hh rn 1 10 Typical Characteristics 1 11 Functional Block Diagram 2 Analog Section Der ee pe as audere dae s ouod ade Reg iens 2 1 Fully Differential Analog Inputs 2 1 1 Analog to Digital Converter Inputs 2 1 2 Window Comparator Inputs 2 1 3 Sign Comparator Inputs 2 2 Analog To Digital 2 2 1 HOLD MOLD x cad 2 2 2 CIO CK it hes 2 2 3 nc MI I 2 2 4 Gain Adjustment 2 2 5 Offset 2 2 6 Transition Noise ieee nete eg pr nee eee 2 3 Sign Comparatots 2 uc edi Cp s D ean he ee J
60. ied with tR tF 5 10 to 90 of BVpp and timed from a voltage level of 2 Refer to CS signal or R W signal whichever occurs last One or more read cycles can be performed in one CS cycle Refer to CS signal or R W signal whichever occurs first Sere 5 a 1 2 3 4 Figure 1 14 Mode 10 Read Access 31 Analog Motor Control Front End with Simultaneous Sampling on 354 EXAS M Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs Texas nrs www ti com SBAS253E MAY 2003 REVISED JULY 2006 3 4 22 Write Timing Characteristics Over recommended operating free air temperature range at 40 C to 85 C AVpp 5V BVpp 3V 5V DsyimeTomRWIOWIOSLQW ow Fetes fre fom GB LOW e WEA _ C UN Width time for WE HIGH 70 Sette areas Aa 1 79 Fo ao ald afer Tg age TW Setup ime dala vaid before edge f ig L8 Des memmWEHIGHwGSGH o L5 Delay ime tom CSHGHTORWHIGH 1 All input signals are specified with tR tF Sns 10 to 90 of BVpp and timed from a voltage level of VjL VjH 2 2 One or more write cycles can be performed in one CS cycle Figure 1 15 Mode 10 Write Access 32 Analog Motor Control Front End with Simultaneous Sampling on Texas lt Seven
61. ix sources are combined into one interrupt signal The interrupt signal is active high when the interrupt pin INT is high one of the six sources is also high To reset an interrupt the Interrupt Register must be read see nterrupt Register section in order to allow the host to determine which source or sources caused the interrupt Reset The ADS7869 can be forced into a reset state in three different ways e Power on e Pulling the RST pin reset pin 79 low e Writing to the Reset Register In addition the digital counters can be reset via the Reset Register without resetting the entire ADS7869 In a reset state the analog inputs are sampled the registers in the register map are forced into their reset values and the FIFO and the counters are cleared One rising clock pulse during a reset condition is necessary to reset the synchronous counters It takes one clock cycle for the ADS7869 to begin the normal operation after the last reset condition is cleared See Figure 1 29 3 10 1 Reset Timing Characteristics Over recommended operating free air temperature range at 40 C to 85 C AVpp 5V BVpp 3V 5V PARAMETER SYMBOL Setup time from RST LOW to rising CLK 10 Hold time from rising CLK to RST HIGH 5 58 Figure 1 29 Timing Diagram of the Reset Signal RST Revision History DATE REV PAGE SECTION DESCRIPTION 7 06 Ordering Information Changed ordering number and transport media NOTE
62. lay time from CS HIGH to output data in tri state mode 4 All input signals are specified with tR 5 10 to 90 of BVpp and timed from a voltage level of Refer to CS signal or RD signal whichever occurs last One or more read cycles can be performed in one CS cycle Refer to CS signal or RD signal whichever occurs first Sere 5 a 1 2 3 4 Figure 1 16 Mode 11 Read Access Standard Mode 33 Analog Motor Control Front End with Simultaneous Sampling on 354 EXAS Capacitors and Three 1MSPS 12 12 Channel ADCs W Texas rs www ti com SBAS253E MAY 2003 REVISED JULY 2006 3 4 32 Write Timing Characteristics Over recommended operating free air temperature range at 40 C to 85 C AVpp 5V BVpp 3V 5V PARAMETER ww Access tne From CS LOW to WR HIGH 1 Width time for WR LOW tw4 Width time for WR HIGH tw Sette assess oases vad af ig yr Setup time daia vaid bere rang ede WR Td Hold tine Dameron 1 All input signals are specified with tR Sns 10 to 90 of BVpp and timed from a voltage level of VIL 2 2 One or more write cycles can be performed in one CS cycle Figure 1 17 Mode 11 Write Access Standard Mode 34 i pna og Motor Control Front End with Simultaneous Sampling on INSTRUMENTS Seven S H Cap
63. mediate conversions the offset error occurs if the gain is modified before the conversion of channels A2 and B2 Offset Adjustment The offset can be adjusted similar to the gain to a 12 bit level with respect to the actual input voltage range of the ADC For example if the input range is 1V the offset can be adjusted in increments of 488uV The maximum adjustment is 12 5 of the input range There is a register inside the digital interface for each input channel This registers store the offset adjustment value for each channel When a channel is selected for conversion the offset is automatically adjusted The selected channel and the related register information must not be changed during the conversion Setting the register to 201 results in a 12 5 adjustment 000 results in no adjustment and 1FF results in a 412 596 adjustment The offset adjustment value 200 is not allowed The offset adjustment cannot be used in VECANA mode A reset condition will set the offset adjustment to Zero i pna og Motor Control Front End with Simultaneous Sampling on INSTRUMENTS Seven S H Capacitors and Three 1MSPS 12 Bit fee i SBAS253E MAY 2003 REVISED JULY 2006 2 2 6 Transition Noise The transition noise of the ADS7869 itself is low as shown in Figure 1 5 Applying a low noise DC input and initiating 8000 conversions generated this histogram o o 2
64. mparator outputs To enable the comparator test the enable part of the register must contain the value This register should not be used in normal operation By reading the Comparator Test register the comparator outputs are sent back in order to allow the host to read the actual comparator outputs in one cycle The format of the output word is shown in Table 1 23 Table 1 23 Comparator Test Register BLUR E EGG OM COR amp amp E avec A em uo vc Ww Uu V Wi bris miris ore rrr E5 0 Input channel address bits 000000 Disable COMPARATOR TEST 001011 Disable COMPARATOR TEST 001100 Enable COMPARATOR TEST write procedure 001101 Disable COMPARATOR TEST 111111 2 Disable COMPARATOR TEST A1 Control bit of position sensor sign comparator A1 output 1 Comparator output A1 set HIGH 0 Comparator output A1 set LOW By reading this bit comparator output B2 is read B1 Control bit of position sensor sign comparator B1 output 1 Comparator output B1 set HIGH 0 Comparator output B1 set LOW A2 Control bit of position sensor sign comparator A2 output 1 Comparator output A2 set HIGH 0 Comparator output A2 set LOW B2 Control bit of position sensor sign comparator B2 output 1 Comparator output B2 set HIGH 0 Comparator output B2 set LOW By reading this bit comparator output 1 is read
65. n new data is written into the FIFO The read pointer will not go beyond the write pointer Both FF and FE go into the Interrupt section The functional block diagram of the FIFO is shown in Figure 1 21 The purpose of the test data is to verify the FIFO structure for the development of an application This is described in the FIFO Test Register section This register should not be used in normal operation FIFO_FULL READ ADC FIFO CONTROL ADC BUSY TEST CLOCK READ and WRITE TEST ENABLE POINTER FIFO FIFO MEMORY SHIFT 32 x 16 REGISTER TEST DATA Figure 1 21 FIFO Block Diagram 50 pna og Motor Control Front End with Simultaneous Sampling on Texas Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs INSTRUMENTS ADS7869 SBAS253E MAY 2003 REVISED JULY 2006 3 7 1 DAV Timing Characteristics 1 Over recommended operating free air temperature range at 40 C to 85 C AVpp 5V BVpp 5V ine Tah Fang CLK orang DAMP Seuptime tom Ro HIGH To nero CK f o Delay ime rom ring SeuptmetromCSHIGHtonenrengGiK Deiay time Fam ising CLK to ising ts Setup ime 5 we Delay time from rising CLK to rising DAVIS PC dd 1 All input signals are specified with tR tF 5ns 10 to 90 of BVpp
66. na Interface section for further information In all other modes there is a register for every input channel inside the digital interface which stores the gain information for any given channel When a particular channel is selected by the application the value of this register is automatically written to the DAC and the DAC output is adjusted to the desired value The DAC settles to this value within 250ns equivalent to the minimum acquisition time The gain information inside the registers is set to zero when a reset condition occurs These registers need to be set to the selected value before the ADCs are used In VECANA mode the DAC is initially set to Full Scale and the differential input range is equal to voltage at the REFIN pin CAUTION An essential offset error occurs when data is held on the sampling capacitors A2 and B2 or AX and BX and the gain of the ADC is modified in intermediate conversions before converting the particular channels A2 and B2 or AX and BX This offset error is possible under two conditions 1 Data can be held on the asynchronous sample and hold capacitors AX and BX with the HOLD2 signal Other channels can be converted before the asynchronous signals AX and BX The offset error occurs if the gain is changed during these conversions 2 With the input commands 4 6 channels A1 and B1 held together with A2 and B2 Channels 1 and B1 will be converted first During this conversion or further inter
67. nel ADCs INSTRUMENTS ADS7869 SBAS253E MAY 2003 REVISED JULY 2006 3 5 Register Map Table 1 10 Register Map Write 16 bit Data ADDRESS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO 00H Unwriteable don t care 01u X X X X X X Channel IU write 10 bit offset DAC value 024 x Channel A1 write 10 bit offset DAC value 03 x Channel A2 write 10 bit offset DAC value 4 x Channel IV write 10 bit offset DAC value 05 x Channel B1 write 10 bit offset DAC value 06 x Channel B2 write 10 bit offset DAC value 074 x Channel IW write 10 bit offset DAC value 08 x Channel write 10 bit offset DAC value 09 X X X X X Channel AN2 write 10 bit offset DAC value x x X X X X Channel AN3 write 10 bit offset DAC value 0B x Channel AX write 10 bit offset DAC value 0C x Channel BX write 10 bit offset DAC value x Channel IU write 12 bit gain DAC value OEy x Channel A1 write 12 bit gain DAC value OFy x Channel 2 write 12 bit gain DAC value 104 x Channel IV write 12 bit gain DAC value 11H x Channel B1 write 12 bit gain DAC value 124 Channel B2 write 12 bit gain DAC value 134 x Channel IW write 12 bit gain DAC value 144 x Channel AN1 write 12 bit gain DAC value 15 x Channel AN2 write 12 bit gain DAC value 16 x Channel AN3 write 12 bit gain DAC value 174 x Channel AX write 12 bit gain DAC value 18u X X x Channel BX wri
68. ns Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security Low Power Wireless www ti com Ipw Telephony www ti com telephony Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2006 Texas Instruments Incorporated i pna og Motor Control Front End with Simultaneous Sampling on INSTRUMENTS Seven S H Capacitors and Three 1MSPS 12 Bit fee 18 SBAS253E MAY 2003 REVISED JULY 2006 Contents mE ee cr 2 ELE 1 4 Ordering Information iD e A Deia a Beia Aa io 1 2 Absolute Maximum Ratings 1 1 3 Recommended Operating Conditions 1 4 Package Dissipation Ratings 1 5 Electrical CharacteristicS ha Baa ide hed ERG e Peed ead 1 6 PoU DIONNE sexs
69. ntial inputs each input is connected to a window comparator and a sign comparator In addition the ADS7869 also offers a very flexible digital interface with a parallel port that can be configured to different standards Furthermore a serial peripheral interface SPI and a specialized serial interface with three data lines VECANAO1 mode are provided This allows the ADS7869 to interface with most digital signal processors DSPs or microcontrollers The chip is specialized for motor control applications For the position sensor analysis two up down counters are added on the silicon This feature ensures that the analog input of the encoder is held at the same point of time as the counter value Encoder Counters Analog Motor Control Front End with Simultaneous Sampling on 4 Seven S H Capacitors and Three 1MSPS 12 12 Channel ADCs 4 Texas ADS7869 www ti com SBAS253E MAY 2003 REVISED JULY 2006 11 ORDERING INFORMATION 1 MAXIMUM INTEGRAL PRODUCT LINEARITY CODES ERROR LSB NO MISSING PACKAGE PACKAGE SPECIFIED ORDERING TRANSPORT LEAD DESIGNATOR TENMDERAINRE NUMBER ERROR LSB RANGE QUANTITY ADS7869IPZT Tray 90 0578691 TQFP 1 40 to 85 C 57869 00 O ADS7869IPZTR Tape em For the most current package and ordering information see the Package Option Addendum located at the end of this data manual 1 2 ABSOLUTE MAXIMUM RATINGS over operating free air temperature range unless
70. olar Offset Match AX and BX Channels Bipolar Offset Error Drift Gain Error Max Input Range Related to REFIN Gain Error Every Other Input Range Gain Error Drift Max Input Range Related to REFIN PSRR Power Supply Rejection Ratio Sampling Dynamics 4 5V AVpp 5 5V tcoNv Conversion Time per ADC 16MHz lt fci k lt 1MHz tago Acquisition Time Throughput Rate Aperture Delay Aperture Delay Matching Aperture Jitter Clock Frequency AC Accuracy Total Harmonic Distortion VIN 2 5Vpp at 10kHz Signal to Noise Distortion VIN 2 5Vpp at 10kHz Signal to Noise Distortion Digital Inputs 2 VIN 2 5Vpp at 10kHz Logic Family Vip High Level Input Voltage Vip Low Level Input Voltage Input Current BVpp to BGND Cj Input Capacitance Digital Outputs 2 Logic Family VOH High Level Output Voltage BVpp 4 5V 100uA VoL Low Level Output Voltage BVpp 4 5V lo 100uA loz High Impedance State Output Current V BVpp to BGND Co Output Capacitance Load Capacitance 1 All values are at Ta 25 C 2 Applies for 5 0V nominal supply 4 5V lt BVpp lt 5 5 3 Applies for 3 0V nominal supply 2 7V lt BVpp lt 3 6V nA Analog Motor Control Front End with Simultaneous Sampling on Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel A
71. ole conversion It is possible to connect HOLD1 and HOLD2 together Analog Motor Control Front End with Simultaneous Sampling on Seven 5 Capacitors and Three MSPS 12 Bit 12 Channel ADCs WO Texas www ti com SBAS253E MAY 2003 REVISED JULY 2006 222 Clock 2 2 3 2 2 4 2 2 5 18 The ADC uses the external clock CLK which needs to be in the range of 1MHz to 16MHz 12 clock cycles are necessary for a conversion with a minimum of four clock cycles for the acquisition Therefore the maximum throughput rate of 1MSPS is achieved with a 16MHz clock and 16 clock cycles per complete conversion cycle The duty cycle should be 5096 however the ADS7869 will still function properly with a duty cycle between 30 and 70 Reset A reset condition stops any ongoing conversion and reconnects the synchronous S Hs to the inputs see the Reset Section Gain Adjustment The output of a 12 bit DAC REF is used as the reference voltage for the ADC There is one DAC for each ADC The voltage range is between OV code 000 and the 2 5V of REFIN code FFF The ADC operates correctly if the selected voltage is in the range of 0 5V to 2 5V The output voltage of the DAC sets the differential input range of the ADC which is REF_ADC The desired input range can be adjusted in 1 22mV steps In the VECANA mode the gain information contained in the digital input word ADIN automatically sets the DAC value See the Veca
72. on is disabled P Write Signal 0 Data Bus is read by ADS7869 at rising edge 1 ADS7869 Write function is disabled Signal is ignored by ADS7869 is ignored by Signal is ignored by ADS7869 11 TMS 0 Data Bus is read by ADS7869 at rising edge of cs ax Read Write Signal 1 Data from ADS7869 is written to the Data Bus 30 i pna og Motor Control Front End with Simultaneous Sampling on INSTRUMENTS Seven S H Capacitors and Three 1MSPS 12 Bit oe SBAS253E MAY 2003 REVISED JULY 2006 3 4 2 Mode 10 Bus Access When M1 1 and 0 mode 10 the host port uses the RD 59 as a read write signal R W and the WR pin 58 as a write enable signal WE The current cycle is only processed when the chip select input CS pin 57 of the ADS7869 is active low R W determines the direction of the transfer during a bus cycle see Figure 1 14 When R W is high data is placed on the databus by ADS7869 according to the address as long as CS is low For a write cycle a low level signal on WE indicates to the ADS7869 that the data on the bus is valid With the rising edge of WE the data is latched into the ADS7869 When the host sets CS to low a valid access to the ADS7869 is detected see Figure 1 15 3 4 2 1 Read Timing Characteristics 1 Over recommended operating free air temperature range at 40 C to 85 C AVpp 5V BVpp 3V 5V 1 9 All input signals are specif
73. onous Analog Input of COS Negative Input Counter Signals of Position Sensors Digital Out Sign of SIN Signal Position Sensor 1 Digital Out Sign of COS Signal Position Sensor 1 Sign of SIN Signal Position Sensor 2 Sign of COS Signal Position Sensor 2 Input Signal SIN to 16 bit Up Down Counter 1 Digital In Input Signal COS to 16 bit Up Down Counter 1 Digital In Input Signal SIN to 16 bit Up Down Counter 2 Digital In Input Signal COS to 16 bit Up Down Counter 2 Analog Input Signals of Phase Currents Analog In Phase U Current Positive Input Analog In Phase U Current Negative Input Analog In Phase V Current Positive Input Analog In Phase W Current Positive Input Analog Motor Control Front End with Simultaneous Sampling on 4 Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs TEXAS ADS7869 INSTRUMENTS SBAS253E MAY 2003 REVISED JULY 2006 TQFP Package SIGNAL PIN NUMBER TYPE DESCRIPTION Comparator Signals of Phase Currents DAOUT 2 Analog Out 8 Bit DAC Output for Over Current Limit Value 9 DAIN 30 Analog In Over Current Limit Value as Input for Window Comparators 34 V Cn Analog In Phase V Current Signal Input for Sign and Window Comparator Negative Input W Cp 35 Analog In Phase W Current Signal Input for Sign and Window Comparator Positive Input W Cn 36 Analog In Phase W Current Signal Input for Sign and Window Comparator Negative Input U COMP 42 Digital Out
74. ored at the addresses OD to 184 The Gain Registers are 12 bits wide The gain value is stored in a straight binary format The data format is shown in Table 1 14 Table 1 14 Gain Registers mes T s Bit 15 12 Always read as 0 don t care at write Bitii 0 7 D11 0 The 12 bits of the gain value 3 64 WINDAC Register 19 The WINDAC Register is located in address 194 WINDAC Register sets the output of the 8 bit DAC used by the window comparators The word is in 8 bit straight binary format The output voltage is a function of the register value and the internal reference voltage See Table 1 3 The format of the data word is shown in Table 1 15 Table 1 15 WINDAC Register m bit 8 Bit 15 8 D7 MSB from DAC input data Bit 7 0 D7 0 The 8 bits input to Digital to Analog Converter 40 Analog Motor Control Front End with Simultaneous Sampling on x TEXAS Seven S H Capacitors and Three 1MSPS 12 Bit oe www ti com SBAS253E MAY 2003 REVISED JULY 2006 3 6 5 Control Register 1A The Control Register is located in address 1 The control register contains the input selection and the DAV control See the F FO section for additional information The format of the Control Register is shown in Table 1 16 For more about the input selection see the Vecana Interface section Table 1 16 Control Registers Biti5 5 3
75. r 1 1224 Interrupt Register ers od he ee ee Bead ee See E EA 1225 Parallel REGISter nett tempe he e ueste nw be ERE ERR b Eres 1226 eset Heglstor us es eese mE ERREUR DRE RA EN EE EAR d 1 27 FIFO 16 bit Data Read cL EE cb dE CL mb viii i pna og Motor Control Front End with Simultaneous Sampling on INSTRUMENTS Seven S H Capacitors and Three 1MSPS 12 Bit fee i SBAS253E MAY 2003 REVISED JULY 2006 FEATURES Seven Simultaneously Sampling Sample and Hold S H Capacitors Fully Differential Inputs Flexible Digital Interface with Four Modes One Mode 100 Software Compatible to VECANAO1 SPI and Two Parallel Modes Two Up Down Counter Modules On Chip 12 Bit System Gain Adjustment for Every Channel 12 Bit Accurate System Offset Adjustment for Every Channel APPLICATIONS Motor Control DESCRIPTION The ADS7869 is a motor control front end that includes three analog to digital converters ADCs with a total of seven sample and hold capacitors and 12 fully differential input channels There are four sign comparators connected to four input channels There are also three additional fully differe
76. r 28H uM 3 7 1 DAV Timing Characteristics Digital Counter Modules 3 8 1 OperatiO x odere doe uude ben d 3 8 2 Digital Noise Filter 3 8 3 Binary Counters and Registers dese tt scie uec dete NE pli EIU 3 10 1 Reset Timing Characteristics Analog Motor Control Front End with Simultaneous Sampling on Texas lt Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel AD Cs www ti com SBAS253E MAY 2003 REVISED JULY 2006 List of Illustrations 1 Typical Motor Control Application 2 Functional Diagram vueetaled edet ior bia doct ben pa pau 3 Equivalent Input Circuit to the ADCs 4 Equivalent Input Circuit of the Window Comparators 5 Histogram of 8000 Conversions senda miter er rnrn rnnr Eas uot 6 Typical Transfer Function of a Sign Comparator
77. riting another pattern to the C bits other than deactivates a reset condition of the counters or a reset condition of the device For more information about reset conditions see the Reset section Table 1 26 Reset Register ses ss s ss 5 s c ce cs c cs cz cr Ports orm bem orto oro pre 7 pre pre bio 57 0 Reset control of entire ADS7869 both digital and analog sections 00000000 No effect on ADS7869 10101001 No effect on ADS7869 10101010 Reset entire ADS7869 10101011 No effect on ADS7869 11111111 No effect on ADS7869 C7 0 Reset control of both counters and related registers of ADS7869 00000000 No effect on ADS7869 10101001 No effect on ADS7869 10101010 Reset both counters in ADS7869 10101011 No effect on ADS7869 11111111 2 No effect on ADS7869 48 Analog Motor Control Front End with Simultaneous Sampling on INST E AS rs Seven S H Capacitors and Three 1MSPS 12 Bit 1 un www ti com SBAS253E MAY 2003 REVISED JULY 2006 3 7 FIFO The FIFO of the ADS7869 is organized as a 32 word ring buffer with 16 bits per word shown in Figure 1 20 Data in FIFO Free Write Pointer Figure 1 20 FIFO Structure The converted data of the ADS7869 is automatically written into the FIFO To control the writing and reading process awrite pointer and a read pointer are use
78. roduct content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 196 by weight in hom*ogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 196 by weight in hom*ogeneous material 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third p
79. rs 12 Channels Positioning Sensori 8 Bit DAC ae Counters T 2 5V Flexible Reference Interface OPA364 ADS7869 Load with Positioning Sensor2 Figure 1 1 Typical Motor Control Application Figure 1 1 shows an example of a typical motor control circuit The IU IV and IW channels measure the currents of the motor The position speed of the motor and load are measured simultaneously by A1 B1 and A2 B2 respectively using resolver or analog encoder sensors The asynchronous inputs AX and BX can be used to capture the reference signal of encoders to derive the absolute position Channel AN1 measures the differential DC link voltage AN3 measures the temperature of the motor An auxiliary voltage can be measured with channel AN2 The counter inputs connect to the appropriate comparator outputs A1 to CNTA1 B1 to CNTB1 and so on The level input of the window comparators DAIN should be connected to the 8 bit DAC output DAOUT 354 pna og INSTRUMENTS Seven www ti com 1 10 TYPICAL CHARACTERISTICS Motor Control Front End with Simultaneous Sampling on Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs ADS7869 SBAS253E MAY 2003 REVISED JULY 2006 At TA 25 AVpp 5V BVpp 3 3V internal 2 5V 16MHz fsamPLE 1 MSPS unless otherwise noted ANALOG SUPPLY CURRENT vs TEMPERATURE 50 48 T
80. t Error Full Scale Error FS Internal Reference Voltage 1LSB louT Output Current Output Settling Time to 0 5LSB no load capacitance Position Sensor Sign Comparator Input Range Lower Voltage of Differential Inputs Offset Range Hysteresis Delay Time TD 1 All values are at Ta 25 C 2 Applies for 5 0V nominal supply 4 5V lt BVpp lt 5 5V 3 Applies for 3 0V nominal supply 2 7V lt BVpp lt 3 6V pna og Motor Control Front End with Simultaneous Sampling on Texas Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs INSTRUMENTS ADS7869 SBAS253E MAY 2003 REVISED JULY 2006 1 5 ELECTRICAL CHARACTERISTICS continued Over recommended operating free air temperature range at 40 C to 85 C 5V BVpp 3 3V VREF internal 2 5V 16MHz fSAMPLE 1 MSPS unless otherwise noted ADS78691 PARAMETER CONDITION 1 UNIT Current Sign Comparator Input Range Lower Voltage of Differential Inputs Offset Range Hysteresis Delay Time Window Comparator Input Range AVpp 0 3 Offset Range 30 Hysteresis 80 Delay Time 16MHz 375 Threshold Voltage Input Range DAIN pin 2 5 1 All values at Ta 25 C 2 Applies for 5 0V nominal supply 4 5V lt BVpp lt 5
81. t present in the Parallel Register the M bit The format of the Parallel Register is shown in Table 1 25 Table 1 25 Parallel Register mo mo Ro f Ro Ro mo ro f Ro mo f Ro me Ro 9 o o ew o o 0 rigor unused ead ss M Set up the type of the parallel interface 1 Parallel interface mode 11 default 0 5320 54 DSP family compatible parallel interface 47 Analog Motor Control Front End with Simultaneous Sampling on S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs TExas AD 7869 www ti com SBAS253E MAY 2003 REVISED JULY 2006 3 6 14 Reset Register 28 The Reset Register in address 28 can either reset the ADS7869 entirely or simply reset the counters Writing an AA pattern to the Cx bits will reset both counter 1 and counter 2 and all registers related to the counters Writing an AA pattern to the Sx bits forces the ADS7869 into a reset state both the digital and the analog sections are reset The Reset Register is a write only register If the Reset Register is read the data 0000 will be received The format of the input word is shown in Table 1 26 To reset the complete ADS7869 the pattern AAAA should be written to the Reset Register Once the Reset Register activates a system reset the register must not be rewritten to in order to deactivate the reset condition W
82. ta from B2 input 0110 Data from IW input 0111 Data from AN1 input 1000 Data from AN2 input 1001 Data from ANS input 1010 Data from AX input 1011 Data from BX input 1100 Unused 1101 Unused 1110 Unused 1111 Unused Bit 11 0 DATA11 0 The output from the ADCs In test mode the upper four bits are copied from Bit 11 of the written data see the Test Register 24 section 39 Analog Motor Control Front End with Simultaneous Sampling on Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs Texas ADS7869 INSTRUMENTS SBAS253E MAY 2003 REVISED JULY 2006 3 6 2 Offset Registers 01 to OC The Offset Registers are stored at the addresses 01 to The Offset Registers are 10 bits wide and represented in the two s complement format The sign bit is copied in bit locations 15 to 10 This copy is only performed by a read access that is bits 15 to 10 must not be correctly set in order to achieve the copy of the sign bit The data format is shown in Table 1 13 The valid offset adjustment values are from 511 2014 to 511 1FFy The value 512 2003 is not allowed Table 1 13 Offset Registers mw RWO RWO D9 19 D9 D9 D9 D2 Dt DO is T5 D9 0 The 10 bits of the offset value 3 6 3 Gain Registers 0D to 18 The Gain Registers are st
83. te 12 bit gain DAC value 19u X X x x X X X Over current write 8 bit window DAC value x 1 x Write 4 bit counter control 1Cy Unwriteable don t care 1Dy Counter 1 write 16 bit value in EDGECOUNT1 counter 1Eu Unwriteable don t care Unwriteable don t care 204 Unwriteable don t care Counter 2 write 16 bit value in EDGECOUNT2 counter 224 Unwriteable don t care 23H Unwriteable don t care 244 write 16 bit value in FIFO_TEST register 25H write 16 bit value in COMP_TEST register 28H write 16 bit value in RESET register 294 3Fy Unwriteable don t care NOTE x means unwriteable don t care 37 Analog Motor Control Front End with Simultaneous Sampling on 354 EXAS Capacitors and Three 1MSPS 12 12 Channel ADCs 5 nrs www ti com SBAS253E MAY 2003 REVISED JULY 2006 Table 1 11 Register Map Read 16 bit Data ADDRESS bis bia bis DTT pio os p 57 bs os bs o bi oo 0 01u Channel IU read 10 bit offset DAC E Ew EC Channel BD read 10 bit offset DAC value x Channel IV read 10 bit offset DAC value xt Channel B1 read 10 bit offset DAC value Channel B2 read 10 bit offset DAC value Channel IW read 10 bit offset DAC value Ez m Channel ANG read 10 bit offset DAC value Channel read 10 bit offset DAC Channel BX read 10 bit offset DAC value Channel IU read 12 bit gain DAC value Channel A1 r
84. trol Front End with Simultaneous Sampling on 4 Seven S H Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs TEXAS ADS7869 INSTRUMENTS SBAS253E MAY 2003 REVISED JULY 2006 3 6 9 Edge Time Period Register 1F and 23 There are two read only shadow registers for the two edge time counters The registers SYEDGTIME1 and SYEDGTIME2 synchronous edge time 1 in address 1 and synchronous edge time 2 in address 23 latch the values from the edge time counters when the synchronous hold signal HOLD1 is set to low The Edge Time Register is described in Table 1 21 Table 1 21 Edge Time Period Register mo ee _ Dis Di2 Dio Pr D7 De D5 J nt f Do Ports bts ors biz pte bts bts Biti5 0 D15 0 The 16 bits of the synchronous latched edge time counters 3 6 10 FIFO Test Register 24 The purpose of the FIFO Test Register in address 24 is to test the FIFO during production test the FIFO is filled with a defined pattern via this register The internal FIFO structure can be verified by reading the patterns of the FIFO data register When the FIFO test is enabled the multiplexers are switched and lead the data of the FIFO test register into the FIFO instead of the normal ADC data to simulate the three ADCs the data is latched into the FIFO thre
85. two edges of the input signals is greater than 4ms at 16MHz Only the time counter keeps its value until a counter reset is performed See the Heset Hegister section for additional information The filtered values of the counter inputs CNTA2 CNTA1 CNTB2 and CNTB1 are sampled with the synchronous signal HOLD1 and are stored in the appropriate bits FB1 FA1 FB2 and FA2 The format of the Counter Control Status Register is described in Table 1 17 Table 1 17 Counter Control Status Register m T 9 9 9 rz re F rs imr bis mz mtr Big PA amp SycwoneusysmbedFUETSQna Bia FBtSyemonwesysmbedFITB sgg Brig FAzSymewoneusysmobedFLENZSQna _ Biz FBESymemomwesysmbedFETEZsnd ___ EO2 EDGECNT2 over or under flow state 1 when EDGECNT1 reached 0 when EDGECNT1 is other than FFFFy TO2 TIMECOUNT2 over or under flow state 1 when TIMECOUNT1 reached 0 when TIMECOUNT1 is other than EO1 EDGECNT1 over or under flow state 1 when EDGECNTO reached 0 when EDGECNTO is other than FFFFy TO1 TIMECOUNT1 over or under flow state 1 when TIMECOUNTO reached 0 when TIMECOUNTO is other than FA2E Enable of digital filter input CNTA2 1 Input signal of CNTA2 will be filtered 0 Input signal of CNTA2 will not be
86. x 4 m o D vli x E Z 2 3 40 25 85 0 1024 2048 3072 4095 Temperature C Code CHANGE IN OFFSET ERROR GAIN ERROR vs GAIN ADJUSTMENT vs OFFSET ADJUSTMENT 4 2 0 15 3 1 0 z 2 05 5 5 0 al 1 2 05 2 0 9 10 0 15 2 0 4095 2997 1899 801 511 0 511 Code Code 12 354 ona og INSTRUMENTS Seven www ti com TYPICAL CHARACTERISTICS Continued Motor Control Front End with Simultaneous Sampling on Capacitors and Three 1MSPS 12 Bit 12 Channel ADCs ADS7869 SBAS253E MAY 2003 REVISED JULY 2006 At TA 25 C AVpp 5V BVpp 3 3V internal 2 5V 16MHz fSAMPLE 1 MSPS unless otherwise noted Offset Error LSB DNL LSB INL LSB DAC OFFSET ERROR vs TEMPERATURE 1 0 40 25 Temperature C DAC DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 0 6 04 a Max 0 2 0 0 2 0 4 0 6 40 25 85 Temperature DAC INTEGRAL LINEARITY ERROR vs TEMPERATURE 0 6 0 3 Max 0 0 3 Min 0 6 40 25 85 Temperature C DNL LSB INL LSB Gain Error a DAC GAIN ERROR vs TEMPERATURE 40 25 85 Temperature C DAC DIFFERENTIAL LINEARITY ERROR vs CODE 0 51 102 153 204 255 DAC INTEGRAL LINEARITY ERROR vs CODE 0 4 0 2 m wl 0 4 13 Analog Motor Control Front End

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